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1 p/n:pm1097 rev. 1.3, nov. 07, 2006 features ? word organization - (16,777,216 + 1,048,576 note ) by 8 bits page size - (512 + 16 note ) by 8 bits block size - (16,384 + 512 note ) by 8 bits note : underlined parts are redundancy and fixed to all ffh. operation mode - read mode (1), read mode (2), read mode (3), reset operating supply voltage : vcc = 2.7~3.6v mx23j12840 128m-bit nand interface xtrarom tm access time - memory cell array to starting address : 7 us (max.) - read cycle time : 50 ns (max.) - re access time : 35 ns (max.) operating supply current - during read : 30 ma (max.) (50 ns cycle operation) - during standby (cmos) : 40 ua (max.) package type - 48-pin tsop(i) (12mmx20mm) xtrarom tm : factory pre-programmed rom with macronix nbit tm technology, supporting short tat process - 0.15um pin description symbol pin name i/o0~i/o7 address input/command inputs/ data outputs cle command latch enable ale address latch enable we write enable re read enable ce chip enable rb ready, /busy pin vcc supply voltage nc no connection gnd ground pin configurations 48 tsop nc nc nc nc nc gnd rb re ce nc nc vcc vss nc nc cle ale we nc nc nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 nc nc nc nc i/o7 i/o6 i/o5 i/o4 nc nc nc vcc gnd nc nc nc i/o3 i/o2 i/o1 i/o0 nc nc nc nc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 mx23j12840 (normal type) order information part no. package grade MX23J12840TC-50g 48 pin tsop (pb-free, rohs) co mmercial MX23J12840TC-50 48 pin tsop co mmercial mx23j12840ti-50g 48 pin tsop (pb-free, rohs) industrial
2 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 block diagram input/output buffer command register read contorol circuit memory cell matrix i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 control logic x-decoder ce cle ale we re vcc rb (open-drain) sense amplifier y-selector data register circuit address register ready/busy control circuit
3 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 memory map the start address (sa) during read operation is specified divided into three areas using three types of read commands. - in read mode (1), start address (sa) is set in area (a). - in read mode (2), start address (sa) is set in area (b). - in read mode (3), start address (sa) is set in area (c). one page consists of a total of 528 bytes broken down into 512 bytes (main memory) and 16 bytes (redundancy). one block consists of 32 pages. caution the data of area (c) is redundancy, which is not programmable and is fixed to all ffh. 1 block =32 pages 512 bytes (main memory) 16 bytes (redundancy) 0 . . . 255 0 1 2 . . 30 31 . . . . . . . . . 32,765 32,766 32,767 256 1 page=528 bytes . . . 511 . 527 1,024 blocks =32,768 pages (b) (a) (c)
4 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 operation modes command input, address input, and serial read are all performed from i/o pins, and the respective statuses are controlled by the cle, ale, we, re, and ce signals. operation mode during serial read mode cle ale ce we re i/o0 - i/o7 data output l l l h l data output output hi-z l l l h h hi-z standby l l h h x hi-z operation mode mode cle ale ce we re command input cycle h l l h address input cycle l h l h serial read cycle l l l h remark : vih or vil command input cycle address input cycle serial read cycle busy cle ce we re i/o0~ i/o7 rb ale
5 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 operation commands the following six operation settings are possible by inputting commands from i/o pins. i/o pin correspondence table during address input cycle (address setting) (1) when 00h or 01h command is set [read mode (1), read mode (2)] command i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1st address cycle a7 a6 a5 a4 a3 a2 a1 a0 2nd address cycle a16 a15 a14 a13 a12 a11 a10 a9 3rd address cycle x a23 a22 a21 a20 a19 a18 a17 (2) when 50h command is set [read mode (3)] command i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1st address cycle x x x x a3 a2 a1 a0 2nd address cycle a16 a15 a14 a13 a12 a11 a10 a9 3rd address cycle x a23 a22 a21 a20 a19 a18 a17 remarks 1. a0 to a23 are internal addresses. 2. internal address a8 is set internally with command 00h or 01h. 3. when 50h command is set [read mode (3)], the i/o4, i/o5, i/o6, and i/o7 inputs of the 1st address cycle are vih or vil. command hex i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 command receivable during busy read mode(1) 00 llllllll read mode(2) 01 lllllllh read mode(3) note1 50 lhlhllll reset note2 ff hhhhhhhh notes: 1. the data output in read mode (3) is all ffh. 2. the only command that can be executed when the device is busy is the reset command. do not set any of the other commands while the device is busy.
6 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 electrical specifications absolute maximum ratings caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol condition rating unit supply voltage vcc -0.5 to +4.6 v input voltage vi -0.3 to vcc+0.3 v input / output voltage vi/o -0.3 to vcc+0.3 (< 4.6) v operating ambient temperature ta -40 to 85 c storage temperature tstg -65 to +150 c capacitance (ta = 25 c) parameter symbol test condition min. typ. max. unit input capacitance ci f = 1 mhz 10 pf output capacitance co 10 pf dc characteristics (ta = -40 to 85 c, vcc = 2.7~3.6v) parameter symbol test conditions min. typ. max. unit high level input voltage vih 2.0 vcc+0.3 v low level input voltage vil -0.3 +0.8 v high level output voltage voh ioh =-400ua 2.4 v low level output voltage vol iol = 2.1 ma 0.4 v input leakage current ili vi = 0 v to vcc 10 ua output leakage current ilo vo = 0 v to vcc 10 ua power supply current in read icco1 ce = vil, iout =0 ma, 30 ma tcycle = 50 ns standby current (cmos) iccs2 ce = vcc-0.2 v 40 ua rb pin output current iol(rb) vol = 0.4 v 8 ma
7 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 parameter symbol min. typ. max. unit cle setup time tcls 0 ns cle hold time tclh 10 ns ce setup time tcs 0 ns ce hold time tch 10 ns write pulse width twp 25 ns ale setup time tals 0 ns ale hold time talh 10 ns data setup time tds 20 ns data hold time tdh 10 ns write cycle time twc 50 ns we high hold time twh 15 ns ready to re falling edge trr 20 ns read pulse width trp 35 ns read cycle time trc 50 ns re access time (serial data access) trea 35 ns ce high hold time for last address in serial read cycle tceh 100 ns re high to output hi-z trhz 10 30 ns ce high to output hi-z tchz 20 ns re high hold time treh 15 ns output hi-z to re falling edge tir 0 ns we high to re low twhr 30 ns memory cell array to starting address tr 7 us we high to busy twb 200 ns ale low to re low (read cycle) tar2 50 ns re last clock rising edge to busy (in sequential read) trb 200 ns ce high to ready (when interrupted by ce in read mode) tcry note 1us device reset time trst 6 us ac characteristics (ta = -40 to 85 c, vcc = 2.7~3.6v) note :tcry (time from ce to ready) depends on the pull-up resister of the rb pin.
8 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 ac test conditions 1.5v 1.5v test points input waveform (rise/fall time < 5ns) 1.5v 1.5v test points output waveform output load : 1 ttl + 100pf input pulse levels : 0.4 ~ 2.4v
9 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 read cycle timing chart (1) (in case of read mode (1)) remarks: 1. start address (sa) specification when read is performed with command 00h. n: 0 to 255 2. the time (tcry) from ce high level until busy is cancelled depends on the pull-up register of the rb output pin. tcls tclh tds tds tdh tdh tdh tdh access page m tds tds twc tar2 trc trp twb treh trb output page m data trhz trhz trea trr trc tceh tcry tchz talh tals twp twh talh tr tcs cle ce 00h a0-a7 a9-a16 a17-a24 dout n n+1 527 dout dout we re i/o0~ i/o7 rb ale tdh tds a25
10 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 read cycle timing chart (2) (in case of read mode (2)) remarks 1. start address (sa) specification when read is performed with command 01h. n: 0 to 255 2. the time (tcry) from ce high level until busy is cancelled depends on the pull-up register of the rb output pin. tcls tclh tds tds tdh tdh tdh tdh access page m tds tds twc tar2 trc trp twb treh trb output page m data trhz trhz trea trr trc tceh tcry tchz talh tals twp twh talh tr tcs cle ce 01h a0-a7 a9-a16 a17-a24 dout 256+n 256+n+1 527 dout dout we re i/o0~ i/o7 rb ale tdh tds a25
11 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 read cycle timing chart (3) (in case of read mode (3)) remarks 1. start address (sa) specification when read is performed with command 50h. n: 0 to 15 2. the start address of area c (redundancy data) is specified with a0 tp a3 during the 1st address cycle. at this time, a4 to a7 are don't care. 3. the time (tcry) from ce high level until busy is cancelled depends on the pull-up register of the rb output pin. tcls tclh tds tds tdh tdh tdh tdh access page m tds tds twc tar2 trc trp twb treh trb output page m data trhz trhz trea trr trc tceh tcry tchz talh tals twp twh talh tr tcs cle ce 50h a0-a3 a9-a16 a17-a24 dout 512+n 512+n+1 527 dout dout we re i/o0~ i/o7 rb ale tdh tds a25
12 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 sequential read in read modes (1), (2), and (3), when a command (00h, 01h, 50h) is input and an address specified, if it is in the block that includes the address that was specified first, the address is automatically incremented and the read operation is continuously performed until the last address in the same block, by inputting the re# clock. at this time, a busy period (tr) occurs after the last address is accessed in a page. note :to perform read again after reading the 527th byte of data of the last page of block, stop the read operation once, and then restart the read operation by inputting again the read command and an address. relationship between command and start address (sa) during sequential read when the "00h" command is set, the start address (sa) is set to area (a). when the "01h" command is set, the start address (sa) is set to area (b). when the "50h" command is set, the start address (sa) is set to area (c). (a) (b) (c) 256 1block =32 pages 0 sa 512 527 sequential read mode (1) (when "00h" command is input) sequential read mode (2) (when "01h" command is input) sequential read mode (3) (when "50h" command is input) note note : when the "50h" command is set, only the (c) area (redundancy data part) is continuously read. (a) (b) (c) 256 sa 512 527 (a) (b) (c) 256 sa 512 527 busy address input command input rb 00h tr busy tr busy in same block (maximum of 32 pages) tr busy tr busy tcry note note busy tr page m data output page m+1 data output output of in last page in block data output address input 01h 50h command input 01h 00h 50h
13 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 sequential read cycle timing chart(1) (in case of read mode (1)) remarks 1.start address (sa) specification when read is performed with command 00h. n:0 to 255. tcls tclh tds tds tdh tdh tdh tdh access page m access page m+1 tds tds twc tar2 trc trp twb treh tr trb output page m data output page m+1 data trr trhz trea trr trc talh tals twp twh talh tr tcs cle ce 00h a0-a7 a9-a16 a17-a24 dout n n+1 527 0 dout dout dout 1 dout we re i/o0~ i/o7 rb ale tdh tds a25
14 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 sequential read cycle timing chart(2) (in case of read mode (2)) remarks 1.start address (sa) specification when read is performed with command 01h. n:0 to 255. tcls tclh tds tds tdh tdh tdh tdh access page m access page m+1 tds tds twc tar2 trc trp twb treh tr trb output page m data output page m+1 data trr trhz trea trr trc talh tals twp twh talh tr tcs cle ce 01h a0-a7 a9-a16 a17-a24 dout 256+n 256+n+1 527 0 dout dout dout 1 dout we re i/o0~ i/o7 rb ale tdh tds a25
15 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 sequential read cycle timing chart(3) (in case of read mode (3)) remarks 1.start address (sa) specification when read is performed with command 50h. n:0 to 15. tcls tclh tds tds tdh tdh tdh tdh access page m access page m+1 tds tds twc tar2 trc trp twb treh tr trb output page m data output page m+1 data trr trhz trea trr trc talh tals twp twh talh tr tcs cle ce 50h a0-a3 a9-a16 a17-a24 dout 512+n 512+n+1 527 512 dout dout dout 513 dout we re i/o0~ i/o7 rb ale tdh tds a25
16 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 reset cycle timing chart tcls tclh tcs tch tals tds tdh twb talh trst twp cle ce ffh we ale rb i/o0~ i/o7
17 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 [usage cautions] (1) rated operation operation using timing other than shown in the timing charts is not guaranteed. (2) commands that can be input the only commands that can be input are 00h, 01h, 50h, and ffh. do not input any other commands. if other commands are input, the subsequent operation is not guaranteed. (3) command limitations during busy period do not input commands other than the reset command (ffh) during the busy period. if a command is input during the busy period, the subsequent operation is not guaranteed. (4) cautions regarding re clock following the last re clock, do not input the re clock until the rb pin changes from busy to ready. do not input the re clock other than during data output. (5) cautions upon power application since the state of the device is undetermined upon power on, input high level to the ce pin and execute the reset command following power on. (6) cautions during read mode perform address input immediately following command input. if address input is done without performing com- mand input first, the correct data cannot be output because the operation mode is undetermined. to execute the read mode after the read mode has been stopped with the reset command (ffh) and ce, input again a command and address. (7) busy output following access of last address in page in read mode after the access to the last address in a page, if the delay (trhch) from re to ce is 30 ns or less, the ready status is maintained and busy is not output by keeping ce high level for a set period (tceh). tceh trhch 527 526 ce re rb
18 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 package information
19 p/n:pm1097 rev. 1.3, nov. 07, 2006 mx23j12840 revision history revision # description page date 1.0 1. changed standby current from 100ua to 40ua p1,6 aug/16/2005 2. removed "advanced information" p1 1.1 1. added "order information" p1 sep/06/2005 1.2 1. removed twhc p7 oct/28/2005 2. modified "read cycle timing chart" and "sequential read cycle timing p9~11 chart" p13~15 1.3 1. added statement p20 no v/07/2006
mx23j12840 m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office : tel:+32-2-456-8020 fax:+32-2-456-8021 hong kong office : tel:+86-512-6258-0888 fax:+86-512-6258-6799 japan office : kawasaki office : tel:+81-44-246-9100 fax:+81-44-246-9105 technical support center : tel:+81-44-246-9875 fax:+81-44-246-9951 singapore office : tel:+65-6346-5505 fax:+65-6348-8096 taipei office : tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-262-8887 fax:+1-408-262-8810 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of macronix's products in the prohibited applications. 20

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